#include <libopencm3/stm32/common/rcc_common_all.h>

Include dependency graph for f1/rcc.h:

Data Structures
struct	rcc_clock_scale

Macros
#define	RCC_CR MMIO32(RCC_BASE + 0x00)

#define	RCC_CFGR MMIO32(RCC_BASE + 0x04)

#define	RCC_CIR MMIO32(RCC_BASE + 0x08)

#define	RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)

#define	RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)

#define	RCC_AHBENR MMIO32(RCC_BASE + 0x14)

#define	RCC_APB2ENR MMIO32(RCC_BASE + 0x18)

#define	RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)

#define	RCC_BDCR MMIO32(RCC_BASE + 0x20)

#define	RCC_CSR MMIO32(RCC_BASE + 0x24)

#define	RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /()/

#define	RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /()/

#define	RCC_CR_PLL3RDY (1 << 29) /* (*) /

#define	RCC_CR_PLL3ON (1 << 28) /* (*) /

#define	RCC_CR_PLL2RDY (1 << 27) /* (*) /

#define	RCC_CR_PLL2ON (1 << 26) /* (*) /

#define	RCC_CR_PLLRDY (1 << 25)

#define	RCC_CR_PLLON (1 << 24)

#define	RCC_CR_CSSON (1 << 19)

#define	RCC_CR_HSEBYP (1 << 18)

#define	RCC_CR_HSERDY (1 << 17)

#define	RCC_CR_HSEON (1 << 16)

#define	RCC_CR_HSIRDY (1 << 1)

#define	RCC_CR_HSION (1 << 0)

#define	RCC_CFGR_OTGFSPRE (1 << 22) /* Connectivity line */

#define	RCC_CFGR_USBPRE (1 << 22) /* LD,MD, HD, XL */

#define	RCC_CFGR_PLLMUL_SHIFT 18

#define	RCC_CFGR_PLLMUL (0xF << RCC_CFGR_PLLMUL_SHIFT)

#define	RCC_CFGR_PLLXTPRE (1 << 17)

#define	RCC_CFGR_PLLSRC (1 << 16)

#define	RCC_CFGR_ADCPRE_SHIFT 14

#define	RCC_CFGR_ADCPRE (3 << RCC_CFGR_ADCPRE_SHIFT)

#define	RCC_CFGR_PPRE2_SHIFT 11

#define	RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT)

#define	RCC_CFGR_PPRE1_SHIFT 8

#define	RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT)

#define	RCC_CFGR_HPRE_SHIFT 4

#define	RCC_CFGR_HPRE (0xF << RCC_CFGR_HPRE_SHIFT)

#define	RCC_CFGR_SWS_SHIFT 2

#define	RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT)

#define	RCC_CFGR_SW_SHIFT 0

#define	RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT)

#define	RCC_CFGR_MCO_SHIFT 24

#define	RCC_CFGR_MCO_MASK 0xf

#define	RCC_CFGR_MCO_NOCLK 0x0

#define	RCC_CFGR_MCO_SYSCLK 0x4

#define	RCC_CFGR_MCO_HSI 0x5

#define	RCC_CFGR_MCO_HSE 0x6

#define	RCC_CFGR_MCO_PLL_DIV2 0x7

#define	RCC_CFGR_MCO_PLL2 0x8 /* (*) /

#define	RCC_CFGR_MCO_PLL3_DIV2 0x9 /* (*) /

#define	RCC_CFGR_MCO_XT1 0xa /* (*) /

#define	RCC_CFGR_MCO_PLL3 0xb /* (*) /

#define	RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0

#define	RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1

#define	RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0

#define	RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5

#define	RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */

#define	RCC_CFGR_PLLXTPRE_HSE_CLK 0x0

#define	RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1

#define	RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0

#define	RCC_CFGR_PLLSRC_HSE_CLK 0x1

#define	RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */

#define	RCC_CFGR_ADCPRE_DIV2 0x0

#define	RCC_CFGR_ADCPRE_DIV4 0x1

#define	RCC_CFGR_ADCPRE_DIV6 0x2

#define	RCC_CFGR_ADCPRE_DIV8 0x3

#define	RCC_CFGR_PPRE2_SHIFT 11

#define	RCC_CFGR_PPRE2_MASK 0x7

#define	RCC_CFGR_PPRE1_SHIFT 8

#define	RCC_CFGR_PPRE1_MASK 0x7

#define	RCC_CFGR_PPRE_NODIV 0x0

#define	RCC_CFGR_PPRE_DIV2 0x4

#define	RCC_CFGR_PPRE_DIV4 0x5

#define	RCC_CFGR_PPRE_DIV8 0x6

#define	RCC_CFGR_PPRE_DIV16 0x7

#define	RCC_CFGR_HPRE_NODIV 0x0

#define	RCC_CFGR_HPRE_DIV2 0x8

#define	RCC_CFGR_HPRE_DIV4 0x9

#define	RCC_CFGR_HPRE_DIV8 0xa

#define	RCC_CFGR_HPRE_DIV16 0xb

#define	RCC_CFGR_HPRE_DIV64 0xc

#define	RCC_CFGR_HPRE_DIV128 0xd

#define	RCC_CFGR_HPRE_DIV256 0xe

#define	RCC_CFGR_HPRE_DIV512 0xf

#define	RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0

#define	RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1

#define	RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2

#define	RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0

#define	RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1

#define	RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2

#define	RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0

#define	RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1

#define	RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2

#define	RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3

#define	RCC_CFGR_PPRE2_HCLK_NODIV 0x0

#define	RCC_CFGR_PPRE2_HCLK_DIV2 0x4

#define	RCC_CFGR_PPRE2_HCLK_DIV4 0x5

#define	RCC_CFGR_PPRE2_HCLK_DIV8 0x6

#define	RCC_CFGR_PPRE2_HCLK_DIV16 0x7

#define	RCC_CFGR_PPRE1_HCLK_NODIV 0x0

#define	RCC_CFGR_PPRE1_HCLK_DIV2 0x4

#define	RCC_CFGR_PPRE1_HCLK_DIV4 0x5

#define	RCC_CFGR_PPRE1_HCLK_DIV8 0x6

#define	RCC_CFGR_PPRE1_HCLK_DIV16 0x7

#define	RCC_CFGR_HPRE_SYSCLK_NODIV 0x0

#define	RCC_CFGR_HPRE_SYSCLK_DIV2 0x8

#define	RCC_CFGR_HPRE_SYSCLK_DIV4 0x9

#define	RCC_CFGR_HPRE_SYSCLK_DIV8 0xa

#define	RCC_CFGR_HPRE_SYSCLK_DIV16 0xb

#define	RCC_CFGR_HPRE_SYSCLK_DIV64 0xc

#define	RCC_CFGR_HPRE_SYSCLK_DIV128 0xd

#define	RCC_CFGR_HPRE_SYSCLK_DIV256 0xe

#define	RCC_CFGR_HPRE_SYSCLK_DIV512 0xf

#define	RCC_CIR_CSSC (1 << 23)

#define	RCC_CIR_PLL3RDYC (1 << 22) /* (*) /

#define	RCC_CIR_PLL2RDYC (1 << 21) /* (*) /

#define	RCC_CIR_PLLRDYC (1 << 20)

#define	RCC_CIR_HSERDYC (1 << 19)

#define	RCC_CIR_HSIRDYC (1 << 18)

#define	RCC_CIR_LSERDYC (1 << 17)

#define	RCC_CIR_LSIRDYC (1 << 16)

#define	RCC_CIR_PLL3RDYIE (1 << 14) /* (*) /

#define	RCC_CIR_PLL2RDYIE (1 << 13) /* (*) /

#define	RCC_CIR_PLLRDYIE (1 << 12)

#define	RCC_CIR_HSERDYIE (1 << 11)

#define	RCC_CIR_HSIRDYIE (1 << 10)

#define	RCC_CIR_LSERDYIE (1 << 9)

#define	RCC_CIR_LSIRDYIE (1 << 8)

#define	RCC_CIR_CSSF (1 << 7)

#define	RCC_CIR_PLL3RDYF (1 << 6) /* (*) /

#define	RCC_CIR_PLL2RDYF (1 << 5) /* (*) /

#define	RCC_CIR_PLLRDYF (1 << 4)

#define	RCC_CIR_HSERDYF (1 << 3)

#define	RCC_CIR_HSIRDYF (1 << 2)

#define	RCC_CIR_LSERDYF (1 << 1)

#define	RCC_CIR_LSIRDYF (1 << 0)

#define	RCC_APB2RSTR_TIM17RST (1 << 18)

#define	RCC_APB2RSTR_TIM16RST (1 << 17)

#define	RCC_APB2RSTR_TIM15RST (1 << 16)

#define	RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */

#define	RCC_APB2RSTR_USART1RST (1 << 14)

#define	RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */

#define	RCC_APB2RSTR_SPI1RST (1 << 12)

#define	RCC_APB2RSTR_TIM1RST (1 << 11)

#define	RCC_APB2RSTR_ADC2RST (1 << 10)

#define	RCC_APB2RSTR_ADC1RST (1 << 9)

#define	RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */

#define	RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */

#define	RCC_APB2RSTR_IOPERST (1 << 6)

#define	RCC_APB2RSTR_IOPDRST (1 << 5)

#define	RCC_APB2RSTR_IOPCRST (1 << 4)

#define	RCC_APB2RSTR_IOPBRST (1 << 3)

#define	RCC_APB2RSTR_IOPARST (1 << 2)

#define	RCC_APB2RSTR_AFIORST (1 << 0)

#define	RCC_APB1RSTR_DACRST (1 << 29)

#define	RCC_APB1RSTR_PWRRST (1 << 28)

#define	RCC_APB1RSTR_BKPRST (1 << 27)

#define	RCC_APB1RSTR_CAN2RST (1 << 26) /* (*) /

#define	RCC_APB1RSTR_CAN1RST (1 << 25) /* (*) /

#define	RCC_APB1RSTR_CANRST

#define	RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */

#define	RCC_APB1RSTR_I2C2RST (1 << 22)

#define	RCC_APB1RSTR_I2C1RST (1 << 21)

#define	RCC_APB1RSTR_UART5RST (1 << 20)

#define	RCC_APB1RSTR_UART4RST (1 << 19)

#define	RCC_APB1RSTR_USART3RST (1 << 18)

#define	RCC_APB1RSTR_USART2RST (1 << 17)

#define	RCC_APB1RSTR_SPI3RST (1 << 15)

#define	RCC_APB1RSTR_SPI2RST (1 << 14)

#define	RCC_APB1RSTR_WWDGRST (1 << 11)

#define	RCC_APB1RSTR_TIM7RST (1 << 5)

#define	RCC_APB1RSTR_TIM6RST (1 << 4)

#define	RCC_APB1RSTR_TIM5RST (1 << 3)

#define	RCC_APB1RSTR_TIM4RST (1 << 2)

#define	RCC_APB1RSTR_TIM3RST (1 << 1)

#define	RCC_APB1RSTR_TIM2RST (1 << 0)

#define	RCC_AHBENR_ETHMACENRX (1 << 16)

#define	RCC_AHBENR_ETHMACENTX (1 << 15)

#define	RCC_AHBENR_ETHMACEN (1 << 14)

#define	RCC_AHBENR_OTGFSEN (1 << 12)

#define	RCC_AHBENR_SDIOEN (1 << 10)

#define	RCC_AHBENR_FSMCEN (1 << 8)

#define	RCC_AHBENR_CRCEN (1 << 6)

#define	RCC_AHBENR_FLITFEN (1 << 4)

#define	RCC_AHBENR_SRAMEN (1 << 2)

#define	RCC_AHBENR_DMA2EN (1 << 1)

#define	RCC_AHBENR_DMA1EN (1 << 0)

#define	RCC_APB2ENR_TIM17EN (1 << 18)

#define	RCC_APB2ENR_TIM16EN (1 << 17)

#define	RCC_APB2ENR_TIM15EN (1 << 16)

#define	RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */

#define	RCC_APB2ENR_USART1EN (1 << 14)

#define	RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */

#define	RCC_APB2ENR_SPI1EN (1 << 12)

#define	RCC_APB2ENR_TIM1EN (1 << 11)

#define	RCC_APB2ENR_ADC2EN (1 << 10)

#define	RCC_APB2ENR_ADC1EN (1 << 9)

#define	RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */

#define	RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */

#define	RCC_APB2ENR_IOPEEN (1 << 6)

#define	RCC_APB2ENR_IOPDEN (1 << 5)

#define	RCC_APB2ENR_IOPCEN (1 << 4)

#define	RCC_APB2ENR_IOPBEN (1 << 3)

#define	RCC_APB2ENR_IOPAEN (1 << 2)

#define	RCC_APB2ENR_AFIOEN (1 << 0)

#define	RCC_APB1ENR_DACEN (1 << 29)

#define	RCC_APB1ENR_PWREN (1 << 28)

#define	RCC_APB1ENR_BKPEN (1 << 27)

#define	RCC_APB1ENR_CAN2EN (1 << 26) /* (*) /

#define	RCC_APB1ENR_CAN1EN (1 << 25) /* (*) /

#define	RCC_APB1ENR_CANEN

#define	RCC_APB1ENR_USBEN (1 << 23) /* (XX) */

#define	RCC_APB1ENR_I2C2EN (1 << 22)

#define	RCC_APB1ENR_I2C1EN (1 << 21)

#define	RCC_APB1ENR_UART5EN (1 << 20)

#define	RCC_APB1ENR_UART4EN (1 << 19)

#define	RCC_APB1ENR_USART3EN (1 << 18)

#define	RCC_APB1ENR_USART2EN (1 << 17)

#define	RCC_APB1ENR_SPI3EN (1 << 15)

#define	RCC_APB1ENR_SPI2EN (1 << 14)

#define	RCC_APB1ENR_WWDGEN (1 << 11)

#define	RCC_APB1ENR_TIM7EN (1 << 5)

#define	RCC_APB1ENR_TIM6EN (1 << 4)

#define	RCC_APB1ENR_TIM5EN (1 << 3)

#define	RCC_APB1ENR_TIM4EN (1 << 2)

#define	RCC_APB1ENR_TIM3EN (1 << 1)

#define	RCC_APB1ENR_TIM2EN (1 << 0)

#define	RCC_BDCR_BDRST (1 << 16)

#define	RCC_BDCR_RTCEN (1 << 15)

#define	RCC_BDCR_LSEBYP (1 << 2)

#define	RCC_BDCR_LSERDY (1 << 1)

#define	RCC_BDCR_LSEON (1 << 0)

#define	RCC_CSR_LPWRRSTF (1 << 31)

#define	RCC_CSR_WWDGRSTF (1 << 30)

#define	RCC_CSR_IWDGRSTF (1 << 29)

#define	RCC_CSR_SFTRSTF (1 << 28)

#define	RCC_CSR_PORRSTF (1 << 27)

#define	RCC_CSR_PINRSTF (1 << 26)

#define	RCC_CSR_RMVF (1 << 24)

#define	RCC_CSR_RESET_FLAGS

#define	RCC_CSR_LSIRDY (1 << 1)

#define	RCC_CSR_LSION (1 << 0)

#define	RCC_AHBRSTR_ETHMACRST (1 << 14)

#define	RCC_AHBRSTR_OTGFSRST (1 << 12)

#define	RCC_CFGR2_I2S3SRC_SYSCLK 0x0

#define	RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1

#define	RCC_CFGR2_I2S2SRC_SYSCLK 0x0

#define	RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1

#define	RCC_CFGR2_I2S2SRC (1 << 17)

#define	RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0

#define	RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1

#define	RCC_CFGR2_PREDIV1SRC (1 << 16)

#define	RCC_CFGR2_PLL3MUL_SHIFT 12

#define	RCC_CFGR2_PLL3MUL (0xF << RCC_CFGR2_PLL3MUL_SHIFT)

#define	RCC_CFGR2_PLL2MUL_SHIFT 8

#define	RCC_CFGR2_PLL2MUL (0xF << RCC_CFGR2_PLL2MUL_SHIFT)

#define	RCC_CFGR2_PREDIV2_SHIFT 4

#define	RCC_CFGR2_PREDIV2 (0xF << RCC_CFGR2_PREDIV2_SHIFT)

#define	RCC_CFGR2_PREDIV1_SHIFT 0

#define	RCC_CFGR2_PREDIV1 (0xF << RCC_CFGR2_PREDIV1_SHIFT)

#define	RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6

#define	RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7

#define	RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8

#define	RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9

#define	RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa

#define	RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb

#define	RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc

#define	RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe

#define	RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf

#define	RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6

#define	RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7

#define	RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8

#define	RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9

#define	RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa

#define	RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb

#define	RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc

#define	RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe

#define	RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf

#define	RCC_CFGR2_PREDIV_NODIV 0x0

#define	RCC_CFGR2_PREDIV_DIV2 0x1

#define	RCC_CFGR2_PREDIV_DIV3 0x2

#define	RCC_CFGR2_PREDIV_DIV4 0x3

#define	RCC_CFGR2_PREDIV_DIV5 0x4

#define	RCC_CFGR2_PREDIV_DIV6 0x5

#define	RCC_CFGR2_PREDIV_DIV7 0x6

#define	RCC_CFGR2_PREDIV_DIV8 0x7

#define	RCC_CFGR2_PREDIV_DIV9 0x8

#define	RCC_CFGR2_PREDIV_DIV10 0x9

#define	RCC_CFGR2_PREDIV_DIV11 0xa

#define	RCC_CFGR2_PREDIV_DIV12 0xb

#define	RCC_CFGR2_PREDIV_DIV13 0xc

#define	RCC_CFGR2_PREDIV_DIV14 0xd

#define	RCC_CFGR2_PREDIV_DIV15 0xe

#define	RCC_CFGR2_PREDIV_DIV16 0xf

#define	RCC_CFGR2_PREDIV2_NODIV 0x0

#define	RCC_CFGR2_PREDIV2_DIV2 0x1

#define	RCC_CFGR2_PREDIV2_DIV3 0x2

#define	RCC_CFGR2_PREDIV2_DIV4 0x3

#define	RCC_CFGR2_PREDIV2_DIV5 0x4

#define	RCC_CFGR2_PREDIV2_DIV6 0x5

#define	RCC_CFGR2_PREDIV2_DIV7 0x6

#define	RCC_CFGR2_PREDIV2_DIV8 0x7

#define	RCC_CFGR2_PREDIV2_DIV9 0x8

#define	RCC_CFGR2_PREDIV2_DIV10 0x9

#define	RCC_CFGR2_PREDIV2_DIV11 0xa

#define	RCC_CFGR2_PREDIV2_DIV12 0xb

#define	RCC_CFGR2_PREDIV2_DIV13 0xc

#define	RCC_CFGR2_PREDIV2_DIV14 0xd

#define	RCC_CFGR2_PREDIV2_DIV15 0xe

#define	RCC_CFGR2_PREDIV2_DIV16 0xf

#define	_REG_BIT(base, bit) (((base) << 5) + (bit))

Enumerations
enum	rcc_osc { RCC_PLL , RCC_PLL2 , RCC_PLL3 , RCC_HSE , RCC_HSI , RCC_LSE , RCC_LSI }

enum	rcc_periph_clken { RCC_DMA1 = _REG_BIT(0x14, 0) , RCC_DMA2 = _REG_BIT(0x14, 1) , RCC_SRAM = _REG_BIT(0x14, 2) , RCC_FLTF = _REG_BIT(0x14, 4) , RCC_CRC = _REG_BIT(0x14, 6) , RCC_FSMC = _REG_BIT(0x14, 8) , RCC_SDIO = _REG_BIT(0x14, 10) , RCC_OTGFS = _REG_BIT(0x14, 12) , RCC_ETHMAC = _REG_BIT(0x14, 14) , RCC_ETHMACTX = _REG_BIT(0x14, 15) , RCC_ETHMACRX = _REG_BIT(0x14, 16) , RCC_AFIO = _REG_BIT(0x18, 0) , RCC_GPIOA = _REG_BIT(0x18, 2) , RCC_GPIOB = _REG_BIT(0x18, 3) , RCC_GPIOC = _REG_BIT(0x18, 4) , RCC_GPIOD = _REG_BIT(0x18, 5) , RCC_GPIOE = _REG_BIT(0x18, 6) , RCC_GPIOF = _REG_BIT(0x18, 7) , RCC_GPIOG = _REG_BIT(0x18, 8) , RCC_ADC1 = _REG_BIT(0x18, 9) , RCC_ADC2 = _REG_BIT(0x18, 10) , RCC_TIM1 = _REG_BIT(0x18, 11) , RCC_SPI1 = _REG_BIT(0x18, 12) , RCC_TIM8 = _REG_BIT(0x18, 13) , RCC_USART1 = _REG_BIT(0x18, 14) , RCC_ADC3 = _REG_BIT(0x18, 15) , RCC_TIM15 = _REG_BIT(0x18, 16) , RCC_TIM16 = _REG_BIT(0x18, 17) , RCC_TIM17 = _REG_BIT(0x18, 18) , RCC_TIM9 = _REG_BIT(0x18, 19) , RCC_TIM10 = _REG_BIT(0x18, 20) , RCC_TIM11 = _REG_BIT(0x18, 21) , RCC_TIM2 = _REG_BIT(0x1C, 0) , RCC_TIM3 = _REG_BIT(0x1C, 1) , RCC_TIM4 = _REG_BIT(0x1C, 2) , RCC_TIM5 = _REG_BIT(0x1C, 3) , RCC_TIM6 = _REG_BIT(0x1C, 4) , RCC_TIM7 = _REG_BIT(0x1C, 5) , RCC_TIM12 = _REG_BIT(0x1C, 6) , RCC_TIM13 = _REG_BIT(0x1C, 7) , RCC_TIM14 = _REG_BIT(0x1C, 8) , RCC_WWDG = _REG_BIT(0x1C, 11) , RCC_SPI2 = _REG_BIT(0x1C, 14) , RCC_SPI3 = _REG_BIT(0x1C, 15) , RCC_USART2 = _REG_BIT(0x1C, 17) , RCC_USART3 = _REG_BIT(0x1C, 18) , RCC_UART4 = _REG_BIT(0x1C, 19) , RCC_UART5 = _REG_BIT(0x1C, 20) , RCC_I2C1 = _REG_BIT(0x1C, 21) , RCC_I2C2 = _REG_BIT(0x1C, 22) , RCC_USB = _REG_BIT(0x1C, 23) , RCC_CAN = _REG_BIT(0x1C, 25) , RCC_CAN1 = _REG_BIT(0x1C, 25) , RCC_CAN2 = _REG_BIT(0x1C, 26) , RCC_BKP = _REG_BIT(0x1C, 27) , RCC_PWR = _REG_BIT(0x1C, 28) , RCC_DAC = _REG_BIT(0x1C, 29) , RCC_CEC = _REG_BIT(0x1C, 30) }

enum	rcc_periph_rst { RST_OTGFS = _REG_BIT(0x28, 12) , RST_ETHMAC = _REG_BIT(0x28, 14) , RST_AFIO = _REG_BIT(0x0c, 0) , RST_GPIOA = _REG_BIT(0x0c, 2) , RST_GPIOB = _REG_BIT(0x0c, 3) , RST_GPIOC = _REG_BIT(0x0c, 4) , RST_GPIOD = _REG_BIT(0x0c, 5) , RST_GPIOE = _REG_BIT(0x0c, 6) , RST_GPIOF = _REG_BIT(0x0c, 7) , RST_GPIOG = _REG_BIT(0x0c, 8) , RST_ADC1 = _REG_BIT(0x0c, 9) , RST_ADC2 = _REG_BIT(0x0c, 10) , RST_TIM1 = _REG_BIT(0x0c, 11) , RST_SPI1 = _REG_BIT(0x0c, 12) , RST_TIM8 = _REG_BIT(0x0c, 13) , RST_USART1 = _REG_BIT(0x0c, 14) , RST_ADC3 = _REG_BIT(0x0c, 15) , RST_TIM15 = _REG_BIT(0x0c, 16) , RST_TIM16 = _REG_BIT(0x0c, 17) , RST_TIM17 = _REG_BIT(0x0c, 18) , RST_TIM9 = _REG_BIT(0x0c, 19) , RST_TIM10 = _REG_BIT(0x0c, 20) , RST_TIM11 = _REG_BIT(0x0c, 21) , RST_TIM2 = _REG_BIT(0x10, 0) , RST_TIM3 = _REG_BIT(0x10, 1) , RST_TIM4 = _REG_BIT(0x10, 2) , RST_TIM5 = _REG_BIT(0x10, 3) , RST_TIM6 = _REG_BIT(0x10, 4) , RST_TIM7 = _REG_BIT(0x10, 5) , RST_TIM12 = _REG_BIT(0x10, 6) , RST_TIM13 = _REG_BIT(0x10, 7) , RST_TIM14 = _REG_BIT(0x10, 8) , RST_WWDG = _REG_BIT(0x10, 11) , RST_SPI2 = _REG_BIT(0x10, 14) , RST_SPI3 = _REG_BIT(0x10, 15) , RST_USART2 = _REG_BIT(0x10, 17) , RST_USART3 = _REG_BIT(0x10, 18) , RST_UART4 = _REG_BIT(0x10, 19) , RST_UART5 = _REG_BIT(0x10, 20) , RST_I2C1 = _REG_BIT(0x10, 21) , RST_I2C2 = _REG_BIT(0x10, 22) , RST_USB = _REG_BIT(0x10, 23) , RST_CAN = _REG_BIT(0x10, 25) , RST_CAN1 = _REG_BIT(0x10, 25) , RST_CAN2 = _REG_BIT(0x10, 26) , RST_BKP = _REG_BIT(0x10, 27) , RST_PWR = _REG_BIT(0x10, 28) , RST_DAC = _REG_BIT(0x10, 29) , RST_CEC = _REG_BIT(0x10, 30) }

enum	rcc_clock_hsi { RCC_CLOCK_HSI_24MHZ , RCC_CLOCK_HSI_48MHZ , RCC_CLOCK_HSI_64MHZ , RCC_CLOCK_HSI_END }

enum	rcc_clock_hse { RCC_CLOCK_HSE12_72MHZ , RCC_CLOCK_HSE16_72MHZ , RCC_CLOCK_HSE25_72MHZ , RCC_CLOCK_HSE8_24MHZ , RCC_CLOCK_HSE8_72MHZ , RCC_CLOCK_HSE_END }

Functions
void	rcc_osc_ready_int_clear (enum rcc_osc osc)
	RCC Clear the Oscillator Ready Interrupt Flag. More...

void	rcc_osc_ready_int_enable (enum rcc_osc osc)
	RCC Enable the Oscillator Ready Interrupt. More...

void	rcc_osc_ready_int_disable (enum rcc_osc osc)
	RCC Disable the Oscillator Ready Interrupt. More...

int	rcc_osc_ready_int_flag (enum rcc_osc osc)
	RCC Read the Oscillator Ready Interrupt Flag. More...

void	rcc_css_int_clear (void)
	RCC Clear the Clock Security System Interrupt Flag. More...

int	rcc_css_int_flag (void)
	RCC Read the Clock Security System Interrupt Flag. More...

void	rcc_osc_on (enum rcc_osc osc)
	RCC Turn on an Oscillator. More...

void	rcc_osc_off (enum rcc_osc osc)
	RCC Turn off an Oscillator. More...

void	rcc_css_enable (void)
	RCC Enable the Clock Security System. More...

void	rcc_css_disable (void)
	RCC Disable the Clock Security System. More...

void	rcc_set_sysclk_source (uint32_t clk)
	RCC Set the Source for the System Clock. More...

void	rcc_set_pll_multiplication_factor (uint32_t mul)
	RCC Set the PLL Multiplication Factor. More...

void	rcc_set_pll2_multiplication_factor (uint32_t mul)
	RCC Set the PLL2 Multiplication Factor. More...

void	rcc_set_pll3_multiplication_factor (uint32_t mul)
	RCC Set the PLL3 Multiplication Factor. More...

void	rcc_set_pll_source (uint32_t pllsrc)
	RCC Set the PLL Clock Source. More...

void	rcc_set_pllxtpre (uint32_t pllxtpre)
	RCC Set the HSE Frequency Divider used as PLL Clock Source. More...

uint32_t	rcc_rtc_clock_enabled_flag (void)
	RCC RTC Clock Enabled Flag. More...

void	rcc_enable_rtc_clock (void)
	RCC Enable the RTC clock. More...

void	rcc_set_rtc_clock_source (enum rcc_osc clock_source)
	RCC Set the Source for the RTC clock. More...

void	rcc_set_adcpre (uint32_t adcpre)
	ADC Setup the A/D Clock. More...

void	rcc_set_ppre2 (uint32_t ppre2)
	RCC Set the APB2 Prescale Factor. More...

void	rcc_set_ppre1 (uint32_t ppre1)
	RCC Set the APB1 Prescale Factor. More...

void	rcc_set_hpre (uint32_t hpre)
	RCC Set the AHB Prescale Factor. More...

void	rcc_set_usbpre (uint32_t usbpre)
	RCC Set the USB Prescale Factor. More...

void	rcc_set_prediv1 (uint32_t prediv)

void	rcc_set_prediv2 (uint32_t prediv)

void	rcc_set_prediv1_source (uint32_t rccsrc)

uint32_t	rcc_system_clock_source (void)
	RCC Get the System Clock Source. More...

void	rcc_clock_setup_in_hsi_out_64mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hsi_configs[RCC_CLOCK_HSI_64MHZ])")

void	rcc_clock_setup_in_hsi_out_48mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hsi_configs[RCC_CLOCK_HSI_48MHZ])")

void	rcc_clock_setup_in_hsi_out_24mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hsi_configs[RCC_CLOCK_HSI_24MHZ])")

void	rcc_clock_setup_in_hse_8mhz_out_24mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hse_configs[RCC_CLOCK_HSE8_24MHZ])")

void	rcc_clock_setup_in_hse_8mhz_out_72mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hse_configs[RCC_CLOCK_HSE8_72MHZ])")

void	rcc_clock_setup_in_hse_12mhz_out_72mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hse_configs[RCC_CLOCK_HSE12_72MHZ])")

void	rcc_clock_setup_in_hse_16mhz_out_72mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hse_configs[RCC_CLOCK_HSE16_72MHZ])")

void	rcc_clock_setup_in_hse_25mhz_out_72mhz (void) LIBOPENCM3_DEPRECATED("use rcc_clock_setup_pll( &rcc_hse_configs[RCC_CLOCK_HSE25_72MHZ])")

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
	Switch sysclock to PLL with the given parameters. More...

void	rcc_backupdomain_reset (void)
	RCC Reset the Backup Domain. More...

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the USART at base specified. More...

uint32_t	rcc_get_timer_clk_freq (uint32_t timer)
	Get the peripheral clock speed for the Timer at base specified. More...

uint32_t	rcc_get_i2c_clk_freq (uint32_t i2c)
	Get the peripheral clock speed for the I2C device at base specified. More...

uint32_t	rcc_get_spi_clk_freq (uint32_t spi)

Variables
uint32_t	rcc_ahb_frequency

uint32_t	rcc_apb1_frequency
	Set the default clock frequencies. More...

uint32_t	rcc_apb2_frequency

const struct rcc_clock_scale	rcc_hsi_configs [RCC_CLOCK_HSI_END]

const struct rcc_clock_scale	rcc_hse_configs [RCC_CLOCK_HSE_END]

Data Structures

Macros

Enumerations

Functions

Variables