libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
adc_common_v1.h
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1/** @addtogroup adc_defines
2
3@author @htmlonly &copy; @endhtmlonly 2014 Karl Palsson <karlp@tweak.net.au>
4
5 */
6
7/*
8 * This file is part of the libopencm3 project.
9 *
10 * Copyright (C) 2014 Karl Palsson <karlp@tweak.net.au>
11 *
12 * This library is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU Lesser General Public License as published by
14 * the Free Software Foundation, either version 3 of the License, or
15 * (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU Lesser General Public License for more details.
21 *
22 * You should have received a copy of the GNU Lesser General Public License
23 * along with this library. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26/**@{*/
27
28/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H
29The order of header inclusion is important. adc.h includes the device
30specific memorymap.h header before including this header file.*/
31
32/** @cond */
33#ifdef LIBOPENCM3_ADC_H
34/** @endcond */
35#ifndef LIBOPENCM3_ADC_COMMON_V1_H
36#define LIBOPENCM3_ADC_COMMON_V1_H
37
38/* --- Convenience macros -------------------------------------------------- */
39
40/* ADC port base addresses (for convenience) */
41/****************************************************************************/
42/** @defgroup adc_reg_base ADC register base addresses
43@ingroup STM32xx_adc_defines
44
45@{*/
46#define ADC1 ADC1_BASE
47/**@}*/
48
49/* --- ADC registers ------------------------------------------------------- */
50
51/* ADC status register (ADC_SR) */
52#define ADC_SR(block) MMIO32((block) + 0x00)
53
54/* ADC control register 1 (ADC_CR1) */
55#define ADC_CR1(block) MMIO32((block) + 0x04)
56
57/* ADC control register 2 (ADC_CR2) */
58#define ADC_CR2(block) MMIO32((block) + 0x08)
59
60/* ADC sample time register 1 (ADC_SMPR1) */
61#define ADC_SMPR1(block) MMIO32((block) + 0x0c)
62
63/* ADC sample time register 2 (ADC_SMPR2) */
64#define ADC_SMPR2(block) MMIO32((block) + 0x10)
65
66#define ADC1_SR ADC_SR(ADC1)
67#define ADC1_CR1 ADC_CR1(ADC1)
68#define ADC1_CR2 ADC_CR2(ADC1)
69#define ADC1_SMPR1 ADC_SMPR1(ADC1)
70#define ADC1_SMPR2 ADC_SMPR2(ADC1)
71
72#define ADC1_JOFR1 ADC_JOFR1(ADC1)
73#define ADC1_JOFR2 ADC_JOFR2(ADC1)
74#define ADC1_JOFR3 ADC_JOFR3(ADC1)
75#define ADC1_JOFR4 ADC_JOFR4(ADC1)
76
77#define ADC1_HTR ADC_HTR(ADC1)
78#define ADC1_LTR ADC_LTR(ADC1)
79
80#define ADC1_SQR1 ADC_SQR1(ADC1)
81#define ADC1_SQR2 ADC_SQR2(ADC1)
82#define ADC1_SQR3 ADC_SQR3(ADC1)
83#define ADC1_JSQR ADC_JSQR(ADC1)
84
85#define ADC1_JDR1 ADC_JDR1(ADC1)
86#define ADC1_JDR2 ADC_JDR2(ADC1)
87#define ADC1_JDR3 ADC_JDR3(ADC1)
88#define ADC1_JDR4 ADC_JDR4(ADC1)
89#define ADC1_DR ADC_DR(ADC1)
90
91#if defined(ADC2_BASE)
92#define ADC2 ADC2_BASE
93#define ADC2_SR ADC_SR(ADC2)
94#define ADC2_CR1 ADC_CR1(ADC2)
95#define ADC2_CR2 ADC_CR2(ADC2)
96#define ADC2_SMPR1 ADC_SMPR1(ADC2)
97#define ADC2_SMPR2 ADC_SMPR2(ADC2)
98
99#define ADC2_JOFR1 ADC_JOFR1(ADC2)
100#define ADC2_JOFR2 ADC_JOFR2(ADC2)
101#define ADC2_JOFR3 ADC_JOFR3(ADC2)
102#define ADC2_JOFR4 ADC_JOFR4(ADC2)
103
104/* ADC watchdog high threshold register (ADC_HTR) */
105#define ADC2_HTR ADC_HTR(ADC2)
106/* ADC watchdog low threshold register (ADC_LTR) */
107#define ADC2_LTR ADC_LTR(ADC2)
108
109/* ADC regular sequence register 1 (ADC_SQR1) */
110#define ADC2_SQR1 ADC_SQR1(ADC2)
111/* ADC regular sequence register 2 (ADC_SQR2) */
112#define ADC2_SQR2 ADC_SQR2(ADC2)
113/* ADC regular sequence register 3 (ADC_SQR3) */
114#define ADC2_SQR3 ADC_SQR3(ADC2)
115/* ADC injected sequence register (ADC_JSQR) */
116#define ADC2_JSQR ADC_JSQR(ADC2)
117
118/* ADC injected data register x (ADC_JDRx) (x=1..4) */
119#define ADC2_JDR1 ADC_JDR1(ADC2)
120#define ADC2_JDR2 ADC_JDR2(ADC2)
121#define ADC2_JDR3 ADC_JDR3(ADC2)
122#define ADC2_JDR4 ADC_JDR4(ADC2)
123/* ADC regular data register (ADC_DR) */
124#define ADC2_DR ADC_DR(ADC2)
125#endif
126
127#if defined(ADC3_BASE)
128#define ADC3 ADC3_BASE
129#define ADC3_SR ADC_SR(ADC3)
130#define ADC3_CR1 ADC_CR1(ADC3)
131#define ADC3_CR2 ADC_CR2(ADC3)
132#define ADC3_SMPR1 ADC_SMPR1(ADC3)
133#define ADC3_SMPR2 ADC_SMPR2(ADC3)
134
135#define ADC3_JOFR1 ADC_JOFR1(ADC3)
136#define ADC3_JOFR2 ADC_JOFR2(ADC3)
137#define ADC3_JOFR3 ADC_JOFR3(ADC3)
138#define ADC3_JOFR4 ADC_JOFR4(ADC3)
139
140#define ADC3_HTR ADC_HTR(ADC3)
141#define ADC3_LTR ADC_LTR(ADC3)
142
143#define ADC3_SQR1 ADC_SQR1(ADC3)
144#define ADC3_SQR2 ADC_SQR2(ADC3)
145#define ADC3_SQR3 ADC_SQR3(ADC3)
146#define ADC3_JSQR ADC_JSQR(ADC3)
147
148#define ADC3_JDR1 ADC_JDR1(ADC3)
149#define ADC3_JDR2 ADC_JDR2(ADC3)
150#define ADC3_JDR3 ADC_JDR3(ADC3)
151#define ADC3_JDR4 ADC_JDR4(ADC3)
152#define ADC3_DR ADC_DR(ADC3)
153#endif
154
155
156
157/* --- ADC Channels ------------------------------------------------------- */
158
159/****************************************************************************/
160/** @defgroup adc_channel ADC Channel Numbers
161@ingroup STM32xx_adc_defines
162
163@{*/
164#define ADC_CHANNEL0 0x00
165#define ADC_CHANNEL1 0x01
166#define ADC_CHANNEL2 0x02
167#define ADC_CHANNEL3 0x03
168#define ADC_CHANNEL4 0x04
169#define ADC_CHANNEL5 0x05
170#define ADC_CHANNEL6 0x06
171#define ADC_CHANNEL7 0x07
172#define ADC_CHANNEL8 0x08
173#define ADC_CHANNEL9 0x09
174#define ADC_CHANNEL10 0x0A
175#define ADC_CHANNEL11 0x0B
176#define ADC_CHANNEL12 0x0C
177#define ADC_CHANNEL13 0x0D
178#define ADC_CHANNEL14 0x0E
179#define ADC_CHANNEL15 0x0F
180#define ADC_CHANNEL16 0x10
181#define ADC_CHANNEL17 0x11
182#define ADC_CHANNEL18 0x12
183/**@}*/
184#define ADC_CHANNEL_MASK 0x1F
185
186
187/* --- ADC_SR values ------------------------------------------------------- */
188/****************************************************************************/
189/** @defgroup adc_sr_values ADC Status Register Flags
190@ingroup STM32xx_adc_defines
191
192@{*/
193
194/* STRT:*//** Regular channel Start flag */
195#define ADC_SR_STRT (1 << 4)
196
197/* JSTRT:*//** Injected channel Start flag */
198#define ADC_SR_JSTRT (1 << 3)
199
200/* JEOC:*//** Injected channel end of conversion */
201#define ADC_SR_JEOC (1 << 2)
202
203/* EOC:*//** End of conversion */
204#define ADC_SR_EOC (1 << 1)
205
206/* AWD:*//** Analog watchdog flag */
207#define ADC_SR_AWD (1 << 0)
208/**@}*/
209
210/* --- ADC_CR1 values ------------------------------------------------------ */
211
212/* AWDEN: Analog watchdog enable on regular channels */
213#define ADC_CR1_AWDEN (1 << 23)
214
215/* JAWDEN: Analog watchdog enable on injected channels */
216#define ADC_CR1_JAWDEN (1 << 22)
217
218/* Note: Bits [21:20] are reserved, and must be kept at reset value. */
219
220
221/* DISCNUM[2:0]: Discontinuous mode channel count. */
222/****************************************************************************/
223/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
224@ingroup STM32_adc_defines
225
226@{*/
227#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
228#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
229#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
230#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13)
231#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13)
232#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13)
233#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13)
234#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
235/**@}*/
236#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
237#define ADC_CR1_DISCNUM_SHIFT 13
238
239/* JDISCEN: */ /** Discontinuous mode on injected channels. */
240#define ADC_CR1_JDISCEN (1 << 12)
241
242/* DISCEN: */ /** Discontinuous mode on regular channels. */
243#define ADC_CR1_DISCEN (1 << 11)
244
245/* JAUTO: */ /** Automatic Injection Group conversion. */
246#define ADC_CR1_JAUTO (1 << 10)
247
248/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */
249#define ADC_CR1_AWDSGL (1 << 9)
250
251/* SCAN: */ /** Scan mode. */
252#define ADC_CR1_SCAN (1 << 8)
253
254/* JEOCIE: */ /** Interrupt enable for injected channels. */
255#define ADC_CR1_JEOCIE (1 << 7)
256
257/* AWDIE: */ /** Analog watchdog interrupt enable. */
258#define ADC_CR1_AWDIE (1 << 6)
259
260/* EOCIE: */ /** Interrupt enable EOC. */
261#define ADC_CR1_EOCIE (1 << 5)
262
263/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
264/* Notes: Depending on part, and ADC peripheral, some channels are connected
265 * to V_SS, or to temperature/reference/battery inputs
266 */
267/****************************************************************************/
268/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */
269/** @defgroup adc_watchdog_channel ADC watchdog channel
270@ingroup STM32xx_adc_defines
271
272@{*/
273#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
274#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
275#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
276#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0)
277#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0)
278#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0)
279#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0)
280#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0)
281#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0)
282#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0)
283#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0)
284#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0)
285#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0)
286#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0)
287#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0)
288#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0)
289#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0)
290#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
291/**@}*/
292#define ADC_CR1_AWDCH_MASK (0x1F << 0)
293#define ADC_CR1_AWDCH_SHIFT 0
294
295/* --- ADC_CR2 values ------------------------------------------------------ */
296
297/* ALIGN: Data alignement. */
298#define ADC_CR2_ALIGN_RIGHT (0 << 11)
299#define ADC_CR2_ALIGN_LEFT (1 << 11)
300#define ADC_CR2_ALIGN (1 << 11)
301
302/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */
303#define ADC_CR2_DMA (1 << 8)
304
305/* CONT: Continuous conversion. */
306#define ADC_CR2_CONT (1 << 1)
307
308/* ADON: A/D converter On/Off. */
309/* Note: If any other bit in this register apart from ADON is changed at the
310 * same time, then conversion is not triggered. This is to prevent triggering
311 * an erroneous conversion.
312 * Conclusion: Must be separately written.
313 */
314#define ADC_CR2_ADON (1 << 0)
315
316/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
317
318#define ADC_JOFFSET_LSB 0
319#define ADC_JOFFSET_MSK 0xfff
320#define ADC_HT_LSB 0
321#define ADC_HT_MSK 0xfff
322#define ADC_LT_LSB 0
323#define ADC_LT_MSK 0xfff
324
325/* --- ADC_SQR1 values ----------------------------------------------------- */
326/* The sequence length field is always in the same place, but sized
327 * differently on various parts */
328#define ADC_SQR1_L_LSB 20
329
330/* --- ADC_JSQR values ----------------------------------------------------- */
331#define ADC_JSQR_JL_LSB 20
332#define ADC_JSQR_JSQ4_LSB 15
333#define ADC_JSQR_JSQ3_LSB 10
334#define ADC_JSQR_JSQ2_LSB 5
335#define ADC_JSQR_JSQ1_LSB 0
336
337/* JL[2:0]: Discontinous mode channel count injected channels. */
338/****************************************************************************/
339/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous injected mode
340@ingroup STM32xx_adc_defines
341
342@{*/
343#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB)
344#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB)
345#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB)
346#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB)
347/**@}*/
348#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
349#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
350#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
351#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
352#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
353
354#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5))
355#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_LSB)
356
357#if (defined(THESE_HAVE_BAD_NAMES_PROBABLY) && (THESE_HAVE_BAD_NAMES_PROBABLY))
358/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
359
360#define ADC_JDATA_LSB 0
361#define ADC_DATA_LSB 0
362#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */
363#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
364#define ADC_DATA_MSK (0xffff << ADC_DA)
365#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
366/* ADC1 only (dual mode) */
367#endif
368
369
370/* --- Function prototypes ------------------------------------------------- */
371
373
374void adc_power_on(uint32_t adc);
375void adc_power_off(uint32_t adc);
376void adc_enable_analog_watchdog_regular(uint32_t adc);
377void adc_disable_analog_watchdog_regular(uint32_t adc);
378void adc_enable_analog_watchdog_injected(uint32_t adc);
379void adc_disable_analog_watchdog_injected(uint32_t adc);
380void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length);
388 uint8_t channel);
389void adc_enable_scan_mode(uint32_t adc);
390void adc_disable_scan_mode(uint32_t adc);
391void adc_enable_eoc_interrupt_injected(uint32_t adc);
392void adc_disable_eoc_interrupt_injected(uint32_t adc);
393void adc_enable_awd_interrupt(uint32_t adc);
394void adc_disable_awd_interrupt(uint32_t adc);
395void adc_enable_eoc_interrupt(uint32_t adc);
396void adc_disable_eoc_interrupt(uint32_t adc);
397void adc_set_left_aligned(uint32_t adc);
398void adc_set_right_aligned(uint32_t adc);
399bool adc_eoc(uint32_t adc);
400bool adc_eoc_injected(uint32_t adc);
401uint32_t adc_read_regular(uint32_t adc);
402uint32_t adc_read_injected(uint32_t adc, uint8_t reg);
403void adc_set_continuous_conversion_mode(uint32_t adc);
404void adc_set_single_conversion_mode(uint32_t adc);
405void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
406void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
407void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
408void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold);
409void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold);
410void adc_start_conversion_regular(uint32_t adc);
411void adc_start_conversion_injected(uint32_t adc);
412void adc_enable_dma(uint32_t adc);
413void adc_disable_dma(uint32_t adc);
414bool adc_get_flag(uint32_t adc, uint32_t flag);
415void adc_clear_flag(uint32_t adc, uint32_t flag);
416
417/* common methods that have slight differences */
418void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time);
419void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
420void adc_disable_external_trigger_regular(uint32_t adc);
422
424
425#endif
426/** @cond */
427#endif
428/** @endcond */
429/**@}*/
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
ADC Set the Sample Time for All Channels.
Definition: adc.c:423
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
ADC Set the Sample Time for a Single Channel.
Definition: adc.c:394
void adc_disable_awd_interrupt(uint32_t adc)
ADC Disable Analog Watchdog Interrupt.
void adc_start_conversion_regular(uint32_t adc)
ADC Software Triggered Conversion on Regular Channels.
void adc_enable_awd_interrupt(uint32_t adc)
ADC Enable Analog Watchdog Interrupt.
bool adc_get_flag(uint32_t adc, uint32_t flag)
Read a Status Flag.
void adc_disable_automatic_injected_group_conversion(uint32_t adc)
ADC Disable Automatic Injected Conversions.
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
ADC Set Analog Watchdog Upper Threshold.
void adc_power_off(uint32_t adc)
ADC Off.
void adc_enable_discontinuous_mode_injected(uint32_t adc)
ADC Enable Discontinuous Mode for Injected Conversions.
void adc_set_continuous_conversion_mode(uint32_t adc)
ADC Enable Continuous Conversion Mode.
void adc_set_single_conversion_mode(uint32_t adc)
ADC Enable Single Conversion Mode.
void adc_disable_discontinuous_mode_regular(uint32_t adc)
ADC Disable Discontinuous Mode for Regular Conversions.
void adc_start_conversion_injected(uint32_t adc)
ADC Software Triggered Conversion on Injected Channels.
void adc_power_on(uint32_t adc)
ADC Power On.
Definition: adc.c:107
uint32_t adc_read_regular(uint32_t adc)
ADC Read from the Regular Conversion Result Register.
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
ADC Enable Discontinuous Mode for Regular Conversions.
void adc_disable_eoc_interrupt_injected(uint32_t adc)
ADC Disable Injected End-Of-Conversion Interrupt.
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
ADC Set an Injected Channel Conversion Sequence.
void adc_enable_eoc_interrupt(uint32_t adc)
ADC Enable Regular End-Of-Conversion Interrupt.
void adc_disable_eoc_interrupt(uint32_t adc)
ADC Disable Regular End-Of-Conversion Interrupt.
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
ADC Enable Analog Watchdog for All Regular and/or Injected Channels.
void adc_disable_scan_mode(uint32_t adc)
ADC Disable Scan Mode.
void adc_disable_dma(uint32_t adc)
ADC Disable DMA Transfers.
void adc_set_left_aligned(uint32_t adc)
ADC Set the Data as Left Aligned.
void adc_disable_external_trigger_injected(uint32_t adc)
ADC Disable an External Trigger for Injected Channels.
Definition: adc.c:306
void adc_set_right_aligned(uint32_t adc)
ADC Set the Data as Right Aligned.
void adc_clear_flag(uint32_t adc, uint32_t flag)
Clear a Status Flag.
void adc_enable_automatic_injected_group_conversion(uint32_t adc)
ADC Enable Automatic Injected Conversions.
void adc_enable_eoc_interrupt_injected(uint32_t adc)
ADC Enable Injected End-Of-Conversion Interrupt.
void adc_enable_analog_watchdog_injected(uint32_t adc)
ADC Enable Analog Watchdog for Injected Conversions.
uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
ADC Read from an Injected Conversion Result Register.
void adc_enable_dma(uint32_t adc)
ADC Enable DMA Transfers.
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
ADC Set the Injected Channel Data Offset.
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel)
ADC Enable Analog Watchdog for a Selected Channel.
void adc_disable_analog_watchdog_injected(uint32_t adc)
ADC Disable Analog Watchdog for Injected Conversions.
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
ADC Set a Regular Channel Conversion Sequence.
void adc_enable_analog_watchdog_regular(uint32_t adc)
ADC Enable Analog Watchdog for Regular Conversions.
bool adc_eoc_injected(uint32_t adc)
ADC Read the End-of-Conversion Flag for Injected Conversion.
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
ADC Set Analog Watchdog Lower Threshold.
bool adc_eoc(uint32_t adc)
ADC Read the End-of-Conversion Flag.
void adc_enable_scan_mode(uint32_t adc)
ADC Set Scan Mode.
void adc_disable_external_trigger_regular(uint32_t adc)
ADC Disable an External Trigger for Regular Channels.
Definition: adc.c:252
void adc_disable_discontinuous_mode_injected(uint32_t adc)
ADC Disable Discontinuous Mode for Injected Conversions.
void adc_disable_analog_watchdog_regular(uint32_t adc)
ADC Disable Analog Watchdog for Regular Conversions.